1. Field of the Invention
The present invention relates to comparator circuits. More specifically, the invention relates to a self-timed differential comparator for applications such as performing a fast comparison of multiple address signals.
2. Description of the Related Art
Microprocessor architectures are continually evolving to improve and extend the capabilities of personal computers. Execution speed, power consumption, and circuit size are aspects of microprocessors and microprocessor performance that are constantly addressed by processor architects and designers in the ongoing quest for an improved product. Execution speed not only depends on the clock rate of a processor, but also upon the speed of interfaces such as cache memories and buses that supply instructions and data for execution by a processor core. The execution speed of microprocessors is heavily analyzed and compared using standard benchmark tests for judging the performance of competing entries into the microprocessor market.
The performance of processors is determined not only on the operating clock speeds of the processors but also upon critical timing paths for handling data in the microprocessor. Data and instruction caches are microprocessor subsystems that are typically in the critical path determining processor performance. Performance depends on a cache controller quickly determining whether the instructions to be executed and the data to be operated upon are currently residing in the cache memory.
What are generally needed in microprocessors are circuits that reduce delays in critical timing paths. What are more specifically needed in microprocessors are memory interface circuits, including cache control circuits, that reduce timing delays in transferring data from memory to processor execution units.